Digital Engineering for MSc - ELE00121M

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  • Department: Electronic Engineering
  • Module co-ordinator: Dr. Gianluca Tempesti
  • Credit value: 10 credits
  • Credit level: M
  • Academic year of delivery: 2019-20
    • See module specification for other years: 2018-19

Module summary

Field Programmable Gate Arrays (FPGA) are a widespread method of implementing fast-running digital circuits on a configurable platform. They can be customised by re-programming their hardware configuration using a Hardware Description Language (HDL). This module introduces tools and methodologies for the design of such advanced digital circuits. Techniques to improve performance (pipelining, clock domain crossing, etc). and to design testable circuits (verification, fault models, design for testability, etc.) will be developed and implemented in lab exercises.

Module will run

Occurrence Teaching cycle
A Spring Term 2019-20

Module aims

Subject content aims:

  • To provide experience in the design of complex FPGA-based circuits, taking into account performance parameters

  • To introduce the use of IP components for circuit design

  • To provide experience in the verification and simulation of complex circuits

  • To introduce concepts relative to test, verification, and fault tolerance in digital circuits

  • To define the requirements for an effective technical documentation of a circuit

Graduate skills aims:

  • To concisely and accurately report the results of experiments

Module learning outcomes

After successful completion of this module, students will:

  • Be able to use and understand the complete design flow (synthesis, place and route, floor-planning, timing analysis, etc.) required to implement complex digital designs

  • Be able to implement and use complex IP modules within a FPGA design

  • Understand advanced circuit design techniques including pipelining, interfacing, and clock manipulation

  • Be able to develop complex HDL testbenches for circuit verification and devise appropriate verification strategies, including post and pre route simulation as well as embedded logic analysers

  • Appreciate the strengths and limitations of fault modelling and detection in digital circuits and integrate built-in test logic in a design

Graduate skills learning outcomes

After successful completion of this module, students will:

  • Be able to concisely and accurately report the results of experiments

Assessment

Task Length % of module mark
Essay/coursework
Digital Engineering - Lab-based Coursework
N/A 100

Special assessment rules

None

Reassessment

Task Length % of module mark
Essay/coursework
Digital Engineering - Lab-based Coursework
N/A 100

Module feedback

'Feedback’ at a university level can be understood as any part of the learning process which is designed to guide your progress through your degree programme. We aim to help you reflect on your own learning and help you feel more clear about your progress through clarifying what is expected of you in both formative and summative assessments. A comprehensive guide to feedback and to forms of feedback is available in the Guide to Assessment Standards, Marking and Feedback. This can be found at https://www.york.ac.uk/students/studying/assessment-and-examination/guide-to-assessment/ The Department of Electronic Engineering aims to provide some form of feedback on all formative and summative assessments that are carried out during the degree programme. In general, feedback on any written work/assignments undertaken will be sufficient so as to indicate the nature of the changes needed in order to improve the work. Students are provided with their examination results within 20 working days of the end of any given examination period. The Department will also endeavour to return all coursework feedback within 20 working days of the submission deadline. The Department would normally expect to adhere to the times given, however, it is possible that exceptional circumstances may delay feedback. The Department will endeavour to keep such delays to a minimum. Please note that any marks released are subject to ratification by the Board of Examiners and Senate. Meetings at the start/end of each term provide you with an opportunity to discuss and reflect with your supervisor on your overall performance to date.

Indicative reading

Notes and readings will be provided in class.



The information on this page is indicative of the module that is currently on offer. The University is constantly exploring ways to enhance and improve its degree programmes and therefore reserves the right to make variations to the content and method of delivery of modules, and to discontinue modules, if such action is reasonably considered to be necessary by the University. Where appropriate, the University will notify and consult with affected students in advance about any changes that are required in line with the University's policy on the Approval of Modifications to Existing Taught Programmes of Study.