Digital Design with HDL - ELE00030I

« Back to module search

  • Department: Electronic Engineering
  • Module co-ordinator: Dr. Gianluca Tempesti
  • Credit value: 10 credits
  • Credit level: I
  • Academic year of delivery: 2019-20

Module summary

This module introduces students to digital design concepts along with the appropriate role of Hardware Description Languages (HDLs) in the modern digital design flow. Particular emphasis will be placed on using HDLs for the synthesis of digital circuits on one side and on the development of appropriate testing through the use of HDL test benches and simulation.

Module will run

Occurrence Teaching cycle
A Autumn Term 2019-20

Module aims

Subject content aims:

  • To introduce the concept and operation of hardware description languages: the basic syntax and structures of an HDL language, the implementation of digital designs using synthesizable HDL, basic simulation tools for digital designs and the concepts of testing and debugging of digital designs

Graduate skills aims:

  • To develop the ability to express algorithms in individual steps, and encode these steps in a programming language

Module learning outcomes

Subject content learning outcomes

After successful completion of this module, students will:

  • Understand and have practice in the design of complex digital circuits using a hierarchical approach
  • Be familiar with the modern design flow for digital circuits and the relevant software tools
  • Be able to design digital circuits using HDL
  • Be able to use simulation to verify the operation of digital circuits
  • Be able to synthesize digital circuits

Graduate skills learning outcomes After successful completion of this module, students will:

  • Have developed the ability to convert complex systems into simple components

Module content

The lab reports are submitted in two instalments so that feedback on the first set can be provided in time for the second hand ­in.

The first hand ­in is in Autumn term week 6, the second in Spring term week 1.

Assessment

Task Length % of module mark
Essay/coursework
Lab Reports
N/A 50
Essay/coursework
Report
N/A 50

Special assessment rules

None

Additional assessment information

Lab Reports are effectively a single assessment split over 2 hand-in dates.

Reassessment

Task Length % of module mark
Essay/coursework
Lab Reports
N/A 100

Module feedback

'Feedback’ at a university level can be understood as any part of the learning process which is designed to guide your progress through your degree programme.  We aim to help you reflect on your own learning and help you feel more clear about your progress through clarifying what is expected of you in both formative and summative assessments.

A comprehensive guide to feedback and to forms of feedback is available in the Guide to Assessment Standards, Marking and Feedback.  This can be found at https://www.york.ac.uk/students/studying/assessment-and-examination/guide-to-assessment/

The Department of Electronic Engineering aims to provide some form of feedback on all formative and summative assessments that are carried out during the degree programme.  In general, feedback on any written work/assignments undertaken will be sufficient so as to indicate the nature of the changes needed in order to improve the work.  Students are provided with their examination results within 20 working days of the end of any given examination period.  The Department will also endeavour to return all coursework feedback within 20 working days of the submission deadline.  The Department would normally expect to adhere to the times given, however, it is possible that exceptional circumstances may delay feedback.  The Department will endeavour to keep such delays to a minimum.  Please note that any marks released are subject to ratification by the Board of Examiners and Senate.  Meetings at the start/end of each term provide you with an opportunity to discuss and reflect with your supervisor on your overall performance to date. 

Indicative reading

To be provided in session



The information on this page is indicative of the module that is currently on offer. The University is constantly exploring ways to enhance and improve its degree programmes and therefore reserves the right to make variations to the content and method of delivery of modules, and to discontinue modules, if such action is reasonably considered to be necessary by the University. Where appropriate, the University will notify and consult with affected students in advance about any changes that are required in line with the University's policy on the Approval of Modifications to Existing Taught Programmes of Study.