Accessibility statement

Digital Design - ELE00067M

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  • Department: Electronic Engineering
  • Module co-ordinator: Dr. Gianluca Tempesti
  • Credit value: 20 credits
  • Credit level: M
  • Academic year of delivery: 2022-23
    • See module specification for other years: 2021-22

Module summary

This module introduces students to digital design concepts along with the appropriate role of Hardware Description Languages (HDLs) in the modern digital design flow. Particular emphasis will be placed on using HDLs for the synthesis of digital circuits on one side and on the development of appropriate testing through the use of HDL testbenches and simulation. The module will then progress to a detailed analysis of the operation and structure of microprocessors, including the design of a simple RISC architecture using VHDL.

Module will run

Occurrence Teaching period
A Autumn Term 2022-23

Module aims

Subject content aims:

  • To introduce the concept and operation of hardware description languages (HDLs) and HDL-based modern digital design flow.
  • To re-establish digital design’s fundamental principles: combinational and sequential logic, finite state machines, and computation building blocks
  • To introduce to the concept of finite state machines with a datapath
  • To analyse in depth the operation and structure of microprocessors, including datapath, control, memory subsystem and peripherals
  • To provide practical experience of working through design problems using modern CAD tools

Graduate skills aims:

  • To develop skills in critically evaluating and synthesising new information based on researched information and writing concise technical reports appropriate for the target audience

Module learning outcomes

Subject content learning outcomes

After successful completion of this module, students will:

  • Understand the digital design concepts and their relationship to practical design
  • Understand principles of various components and know how to use them
  • Be able to design and simulate a variety of digital circuits with HDL
  • Be able to design, implement and test general-purpose and application-specific processor architectures
  • Be able to use modern CAD tools for design capture, modelling, simulation, synthesis, functional verification and other aspects of the digital design flow.

Graduate skills learning outcomes

After successful completion of this module, students will:

  • Be able to construct concise technical reports that critically evaluate and synthesise new information based on research, appropriate for the target audience

  • To develop individual and group skills in the design, test, and verification of digital circuits

Assessment

Task Length % of module mark
Essay/coursework
Individual Assignment 1		 N/A 25
Essay/coursework
Individual Assignment 2		 N/A 75

Special assessment rules

None

Reassessment

Task Length % of module mark
Essay/coursework
Individual Assignment 1		 N/A 25
Essay/coursework
Individual Assignment 2		 N/A 75

Module feedback

'Feedback’ at a university level can be understood as any part of the learning process which is designed to guide your progress through your degree programme.  We aim to help you reflect on your own learning and help you feel more clear about your progress through clarifying what is expected of you in both formative and summative assessments.

A comprehensive guide to feedback and to forms of feedback is available in the Guide to Assessment Standards, Marking and Feedback.  This can be found at https://www.york.ac.uk/students/studying/assessment-and-examination/guide-to-assessment/

The Department of Electronic Engineering aims to provide some form of feedback on all formative and summative assessments that are carried out during the degree programme.  In general, feedback on any written work/assignments undertaken will be sufficient so as to indicate the nature of the changes needed in order to improve the work.  Students are provided with their examination results within 20 working days of the end of any given examination period.  The Department will also endeavour to return all coursework feedback within 20 working days of the submission deadline.  The Department would normally expect to adhere to the times given, however, it is possible that exceptional circumstances may delay feedback.  The Department will endeavour to keep such delays to a minimum.  Please note that any marks released are subject to ratification by the Board of Examiners and Senate.  Meetings at the start/end of each term provide you with an opportunity to discuss and reflect with your supervisor on your overall performance to date. 

Indicative reading

Roth, CH, Digital Systems Design using VHDL, PWS Publishing, 1998. ISBN 0-534-95099-X.

Pedroni, VA, Circuit Design and Simulation with VHDL, MIT press, 2010. ISBN 978 026 201 4335

Smith, John S. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997, ISBN: 978-020-150-0226


The information on this page is indicative of the module that is currently on offer. The University is constantly exploring ways to enhance and improve its degree programmes and therefore reserves the right to make variations to the content and method of delivery of modules, and to discontinue modules, if such action is reasonably considered to be necessary by the University. Where appropriate, the University will notify and consult with affected students in advance about any changes that are required in line with the University's policy on the Approval of Modifications to Existing Taught Programmes of Study.