Posted on 30 April 2015
Over the past 20 years, computing devices have rapidly improved in performance and function density enabled by the continuous shrinking of technology sizes. However, as device sizes have now approached atomistic scales the statistical nature of intrinsic device variations becomes prevalent. Fabrication yields decrease drastically and failure rates increase significantly as a result, because every physical instance of a design behaves in a stochastically different manner. Despite great efforts and advances in technology and novel materials the laws of Physics and Chemistry will always apply and intrinsic variability, device mismatch and noise will always be present at the lowest levels of any system. Therefore, large complex systems need to be designed taking certain levels of ‘uncertainty’ at lower levels into consideration. In turn, when assembling larger entities from smaller components, a certain amount of ‘uncertainty’ in behaviour needs to be expected. In this vein, it is as much about understanding, modelling and predicting variability and noise, as it is about thinking about ways to ‘embrace intrinsic variations’ and build systems that can robustly function despite these effects.
The workshop aims to highlight and address these challenges. It brings together people from different strands of device and circuit design, and provides a venue to collectively talk about emerging trends and the future development of the field. The technical programme will address a diverse range of research areas related to ‘designing with uncertainty’, such as: