The CHERI capability model: Revisiting RISC in an age of risk

Monday 15 May 2017, 2.00PM to 15:00

Speaker(s): Professor Simon Moore, University of Cambridge


Motivated by contemporary security challenges, we reevaluate and refine capability-based addressing for the RISC era. We present CHERI, a hybrid capability model that extends the 64-bit MIPS ISA with byte-granularity memory protection. We demonstrate that CHERI enables language memory model enforcement and fault isolation in hardware rather than software, and that the CHERI mechanisms are easily adopted by existing programs for efficient in-program memory safety. In contrast to past capability models, CHERI complements, rather than replaces, the ubiquitous page-based protection mechanism, providing a migration path towards deconflating data-structure protection and OS memory management. Furthermore, CHERI adheres to a strict RISC philosophy: it maintains a load-store architecture and requires only singlecycle instructions, and supplies protection primitives to the compiler, language runtime, and operating system. We demonstrate a mature FPGA implementation that runs the FreeBSD operating system with a full range of software and an open-source application suite compiled with an extended LLVM to use CHERI memory protection.


Simon Moore is a Professor of Computer Engineering at the University of Cambridge Computer Laboratory in England, where he undertakes research and teaching in the general area of computer design with particular interests in secure and rigorously-engineered computer architecture. Professor Moore is the senior member of the Computer Architecture research group. Simon is an alumni of York having completed his MEng in Computer Systems in Software Engineering.



Location: PL002

Admission: Free


Telephone: 4485

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Please contact Helen Fagan, Postgraduate Office, for more information.


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